/*!
    \file    usbd_hw.h
    \brief   usbd hardware configure file

    \version 2020-08-01, V3.0.0, firmware for GD32F30x
    \version 2022-06-10, V3.1.0, firmware for GD32F30x
*/

/*
    Copyright (c) 2022, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

#ifndef __USBD_CONF_H
#define __USBD_CONF_H

#include "gd32f30x.h"


#define USBD_CFG_MAX_NUM                    1
#define USBD_ITF_MAX_NUM                    3


/* bInterfaceNumber */
#define USBD_MSC_INTERFACE                  0
#define CDC_ACM_CMD_INTERFACE               1
#define CDC_ACM_DATA_INTERFACE              2


/* endpoint count used by the X device */
#define EP_COUNT                            6

#define MSC_IN_EP                           EP_IN(1)
#define MSC_OUT_EP                          EP_OUT(2)
#define CDC_ACM_CMD_EP                      EP_IN(3)
#define CDC_ACM_IN_EP                       EP_IN(4)
#define CDC_ACM_OUT_EP                      EP_OUT(5)

/* bEndpoint data size */
#define CDC_ACM_CMD_PACKET_SIZE             8
#define CDC_ACM_DATA_PACKET_SIZE            64
#define MSC_DATA_PACKET_SIZE                64

/* endpoint0, Rx/Tx buffers address offset */
#define EP0_TX_ADDR                         0x40
#define EP0_RX_ADDR                         0x80

/* MSC data Tx/Rx buffer address offset */
#define MSC_BULK_TX_ADDR                    0xC0
#define MSC_BULK_RX_ADDR                    0x100

/* CDC data Tx/Rx buffer address offset */
#define CDC_ACM_BULK_RX_ADDR                0x140
#define CDC_ACM_BULK_TX_ADDR                0x180
/* CDC command Tx buffer address offset */
#define CDC_ACM_INT_TX_ADDR                 0x1C0

/* MSC config */
#define MEM_LUN_NUM                         2
#define MSC_MEDIA_PACKET_SIZE               512


#define USB_PULLUP                         GPIOA
#define USB_PULLUP_PIN                     GPIO_PIN_8
#define RCU_PULLUP                         RCU_GPIOA


/* base address offset of the allocation buffer, used for buffer descriptor table and packet memory */
#define BTABLE_OFFSET                       (0x0000)

#endif /* __USBD_CONF_H */
